DocumentCode
968818
Title
Punchthrough current for submicrometer MOSFETs in CMOS VLSI
Author
Zhu, Jun ; Martin, Russel A. ; Chen, John Y.
Volume
35
Issue
2
fYear
1988
fDate
2/1/1988 12:00:00 AM
Firstpage
145
Lastpage
151
Abstract
Simulated and measured data show that drain-induced barrier lowering (DIBL) in buried-channel MOSFETs is different from that in surface channel (SC) MOSFETs. This is explained by the differences between channel current paths and channel potential distribution. A new parameter, defined as the incremental voltage that the drain can sustain before the punchthrough current increases by an order of magnitude, is used to indicate the rate of increase of punchthrough current and is a measure of DIBL
Keywords
CMOS integrated circuits; VLSI; insulated gate field effect transistors; semiconductor device models; 2D modelling; CMOS VLSI; buried-channel MOSFETs; channel current paths; channel potential distribution; drain-induced barrier lowering; incremental voltage; punchthrough current; submicron MOSFET; CMOS integrated circuits; CMOS technology; Charge carrier density; Electrons; Electrostatics; Integrated circuit modeling; Laboratories; MOSFET circuits; Very large scale integration; Voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.2433
Filename
2433
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