On-Chip Interconnection Networks of the TRIPS Chip

Author

Gratz, Paul ; Changkyu Kim ; Sankaralingam, K. ; Hanson, H. ; Shivakumar, P. ; Keckler, Stephen W. ; Burger, Danilo

Author_Institution

Univ. of Texas at Austin, Austin

Volume

27

Issue

5

fYear

2007

Firstpage

41

Lastpage

50

Abstract

The TRIPS chip prototypes two networks on chip to demonstrate the viability of a routed interconnection fabric for memory and operand traffic. In a 170-million-transistor custom ASIC chip, these NoCs provide system performance within 28 percent of ideal noncontended networks at a cost of 20 percent of the die area. our experience shows that NoCs are area- and complexity-efficient means of providing high-bandwidth, low-latency on-chip communication.

Keywords

multiprocessor interconnection networks; network routing; network-on-chip; ASIC chip; NoC; TRIPS chip; memory traffic; network-on-chip; operand traffic; routed interconnection network; Application specific integrated circuits; Multiprocessor interconnection networks; Network interfaces; Network-on-a-chip; Protocols; System-on-a-chip; Telecommunication traffic; communication; distributed architectures; multicore architectures; networking; on-chip interconnection networks; packet-switching networks;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/MM.2007.4378782

Filename

4378782