• DocumentCode
    969606
  • Title

    Signature Analysis of Dispatch Schemes in Wafer Fabrication

  • Author

    Dayhoff, Judith E. ; Atherton, Robert W.

  • Author_Institution
    Judith Dayhoff & Associates, Inc., CA
  • Volume
    9
  • Issue
    4
  • fYear
    1986
  • fDate
    12/1/1986 12:00:00 AM
  • Firstpage
    518
  • Lastpage
    525
  • Abstract
    Signature analysis is used to characterize lot dispatch priority schemes in wafer fabrication, a complex manufacturing operation. A number of idealized dispatch schemes are evaluated using a comprehensive assessment criterion. The production system analyzed in this paper is large in comparison to previous studies on manufacturing scheduling. Real dispatch schemes depend strongly on the characteristics of human implementation. Signature analysis provides the basis for measuring organizational performance by comparing formal dispatch schemes with each other and with actual dispatch schemes used in wafer fabrication.
  • Keywords
    Integrated circuit fabrication; Manufacturing; Fabrication; Integrated circuit manufacture; Integrated circuit modeling; Job shop scheduling; Manufacturing processes; Operations research; Production facilities; Production systems; Semiconductor device modeling; Semiconductor process modeling;
  • fLanguage
    English
  • Journal_Title
    Components, Hybrids, and Manufacturing Technology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0148-6411
  • Type

    jour

  • DOI
    10.1109/TCHMT.1986.1136660
  • Filename
    1136660