• DocumentCode
    969607
  • Title

    A 5-GHz Mesh Interconnect for a Teraflops Processor

  • Author

    Hoskote, Y. ; Vangal, S. ; Singh, A. ; Borkar, N. ; Borkar, S.

  • Author_Institution
    Intel Corp., Hillsboro
  • Volume
    27
  • Issue
    5
  • fYear
    2007
  • Firstpage
    51
  • Lastpage
    61
  • Abstract
    A multicore processor in 65-Nm technology with 80 single-precision, floatingpoint cores delivers performance in excess of a Teraflops while consuming less than 100 W. A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores. The network delivers a bisection bandwidth of 2.56 Terabits per second and a per hop fall-through latency of 1 nanosecond.
  • Keywords
    logic design; multiprocessor interconnection networks; network-on-chip; 2D on-die mesh interconnection network; Teraflops processor; bisection bandwidth; frequency 5 GHz; multicore processor; network-on-chip; Bandwidth; Delay; Engines; Intelligent networks; Multiprocessor interconnection networks; Network-on-a-chip; Power dissipation; Scalability; CMOS digital integrated circuits; crossbar; interconnection fabric; mesh; network on chip; router;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2007.4378783
  • Filename
    4378783
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=969607