• DocumentCode
    969618
  • Title

    Architecture of the Scalable Communications Core´s Network on Chip

  • Author

    llitzky, D.A. ; Hoffman, Jeffrey D. ; Chun, Anthony ; Esparza, Brando Perez

  • Author_Institution
    Intel´´s Commun. Res. Center, Guadalajara
  • Volume
    27
  • Issue
    5
  • fYear
    2007
  • Firstpage
    62
  • Lastpage
    74
  • Abstract
    The SCC is a flexible and energy-and area-efficient baseband processor for concurrent multiple wireless protocols. Its architecture consists of coarse grained, heterogeneous, programmable accelerators connected via a packet-based, 3-ary 2-cube network on chip. The NOC supports goals of flexibility, scalability, and extensibility, and it meets stringent latency and throughput requirements.
  • Keywords
    network-on-chip; protocols; NoC; SCC network on chip; baseband processor; concurrent multiple wireless protocol; programmable accelerator; scalable communications core; Access protocols; Baseband; Computer architecture; Delay; Digital TV; Hardware; Network-on-a-chip; Throughput; WiMAX; Wireless application protocol; communication; multicore architectures; networking; on-chip interconnection networks; parallel architectures; wide-area networks; wireless;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2007.4378784
  • Filename
    4378784
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=969618