DocumentCode
969655
Title
Research Challenges for On-Chip Interconnection Networks
Author
Owens, J.D. ; Dally, W.J. ; Ho, R. ; Jayasimha, D.N. ; Keckler, Stephen W. ; Li-Shiuan Peh
Author_Institution
Univ. of California, Davis
Volume
27
Issue
5
fYear
2007
Firstpage
96
Lastpage
108
Abstract
On-chip interconnection networks are rapidly becoming a key enabling technology for commodity multicore processors and SoCs common in consumer embedded systems, the National Science Foundation initiated a workshop that addressed upcoming research issues in OCIN technology, design, and implementation and set a direction for researchers in the field.
Keywords
multiprocessor interconnection networks; research and development; system-on-chip; National Science Foundation; SoCs; commodity multicore processors; consumer embedded systems; on-chip interconnection networks; CMOS technology; Circuits; Delay; Design automation; Intelligent networks; Microarchitecture; Multicore processing; Multiprocessor interconnection networks; Network-on-a-chip; System-on-a-chip; embedded systems; multicore architectures; network on chip; on-chip interconnection networks; system on chip;
fLanguage
English
Journal_Title
Micro, IEEE
Publisher
ieee
ISSN
0272-1732
Type
jour
DOI
10.1109/MM.2007.4378787
Filename
4378787
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