Low-Power and Compact CMOS APS Circuits for Hybrid Cryogenic Infrared Fast Imaging

This brief presents a complete set of CMOS basic building blocks for low-cost scanning infrared (IR) cryogenic imagers. Low-power and compact novel circuits are proposed for single-capacitor integration and correlated double sampling, embedded pixel test, pixel charge-multiplexing and video composition and buffering. In order to validate the new basic building blocks, experimental results are reported in standard 0.35-mum CMOS technology for a 50 mum x 100 mum active pixel cell operating at 77 K. Based on the proposed circuits, IR imagers capable of capturing up to 256 x 2560 pixels at 25 fps can be implemented.