Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers

Author

Pugliese, Andrea ; Cappuccino, Gregorio ; Cocorullo, Giuseppe

Author_Institution

Calabria Univ., Rende

Volume

55

Issue

1

fYear

2008

Firstpage

1

Lastpage

5

Abstract

Low-power, low-voltage, and high-performance requirements are badly needed for operational amplifiers (op-amps) in modern applications. In this brief, a design method for minimizing the settling time in three-stage nested-Miller schemes is presented. As an application example, a CMOS 0.35-mum voltage follower with 115-dB dc gain and fastest step response to 1% accuracy level, is designed. Circuital simulations demonstrate that the proposed procedure allows the amplifier settling-time/power-consumption ratio to be significantly improved with respect to conventionally designed op-amps.

Keywords

CMOS analogue integrated circuits; circuit simulation; network synthesis; operational amplifiers; CMOS voltage follower; circuital simulations; operational amplifiers; settling time minimization; size 0.35 mum; three-stage nested-Miller amplifiers; CMOS technology; Capacitance; Circuit simulation; Design methodology; Frequency; Minimization; Operational amplifiers; Power amplifiers; Transfer functions; Voltage; Analog design; frequency compensation; operational amplifiers (op-amps); transient response;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2007.906086

Filename

4380295