Delay optimization of digital CMOS VLSI circuits by transistor reordering

Author

Carlson, Bradley S. ; Lee, Shu-Juch

Author_Institution

Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA

Volume

14

Issue

10

fYear

1995

fDate

10/1/1995 12:00:00 AM

Firstpage

1183

Lastpage

1192

Abstract

In this paper the effects of transistor reordering on the delay of CMOS digital circuits are investigated, and an efficient method which uses transistor reordering for the delay optimization of CMOS circuits is presented. The proposed technique achieves significant reduction in propagation delays with little effect on layout area and power dissipation. The technique can be coupled with transistor sizing to achieve the desired improvement in circuit delay. Experimental results for benchmark circuits are given in 2.0, 1.2, and 0.8 μm CMOS technologies. The average improvement in delay for the 20 benchmarks used in this paper is 9.1%

Keywords

CMOS digital integrated circuits; VLSI; circuit optimisation; delays; 0.8 micron; 1.2 micron; 2.0 micron; delay optimization; digital CMOS VLSI circuits; layout area; power dissipation; transistor reordering; transistor sizing; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; Circuit faults; Delay effects; Digital circuits; Logic gates; MOSFETs; Propagation delay; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.466335

Filename

466335