Active timing multilevel fault-simulation with switch-level accuracy

Author

Meyer, Wolfgang ; Camposano, Raul

Author_Institution

Inst. for Syst. Design Technol., GMD, Sankt Augustin, Germany

Volume

14

Issue

10

fYear

1995

fDate

10/1/1995 12:00:00 AM

Firstpage

1241

Lastpage

1256

Abstract

This paper describes SATISFAULT, a new hierarchical multilevel fault simulator with switch-level fault models and switch-level accuracy. SATISFAULT´s intelligent scheduling mechanism switches between the abstraction levels to force simulation at the highest, thus fastest, possible level of abstraction without losing switch-level accuracy. The simulation algorithm is based on single fault-propagation for active faults. It deals with multiple abstraction levels and supports the inertial delay model. As a result, even large circuits may be fault-simulated accurately with all faults injected at the switch-level. Complete fault-simulation of all transistors stuck-on and stuck-open of circuits up to 105000 transistors including faults inside flip-flops is possible in reasonable time. In addition, SATISFAULT is also capable of simulating bridging faults for IddQ detectability

Keywords

circuit analysis computing; fault diagnosis; flip-flops; switching circuits; timing; IddQ detectability; SATISFAULT; abstraction; active faults; active timing; algorithm; bridging faults; circuits; hierarchical multilevel fault simulator; inertial delay model; intelligent scheduling; single fault propagation; stuck-on faults; stuck-open faults; switch-level accuracy; switch-level fault models; transistors; Circuit faults; Circuit simulation; Circuit testing; Costs; Delay; Flip-flops; Switches; Switching circuits; Test pattern generators; Timing;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.466340

Filename

466340