DocumentCode :
970851
Title :
VVMOS power transistors: upper and lower bounds of the on-resistance
Author :
Tsibukis, T.D. ; Kriezis, E.E.
Author_Institution :
University of Thessaloniki, Thessaloniki, Greece
Volume :
17
Issue :
10
fYear :
1981
Firstpage :
353
Lastpage :
355
Abstract :
The estimation of the n¿ drift layer resistance Rn¿ of power VVMOS (V-groove vertical-geometry power MOST) devices is treated in the letter. The obtained results, based on the possibility of defining upper and lower bounds of the accurate value, are compared with experimental and theoretical results of other methods.
Keywords :
electric resistance; insulated gate field effect transistors; power transistors; semiconductor device models; V-groove VMOS, transistors; VVMOS power transistors; n- drift layer resistance; on-resistance bounds; semiconductor device models;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19810249
Filename :
4245718
Link To Document :
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