Faster parallel multiplier

Realization of a parallel multiplier has been considered in a paper by Dadda [1] who has proposed various schemes to get the product using (3, 2), (2, 2) counters, and carry look-ahead adders. The complexity of the carry look-ahead adder in terms of number of two-input gates increases with the length of the adder which in effect reduces the speed. This letter presents an approach that reduces the length of carry look-ahead adder, thus increasing the computation speed with a reduction in logic complexity.