Title :
Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs
Author :
Allstot, David J. ; Chee, San-Hwa ; Kiaei, Sayfe ; Shrivastawa, Manu
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fDate :
9/1/1993 12:00:00 AM
Abstract :
CMOS folded source-coupled logic (FSCL) uses a smaller logic voltage swing (ΔVL≃0.2 Vdd) than conventional static logic and achieves a smaller power-delay product at high operating frequencies. By using current-steering techniques in fully-differential FSCL circuits to maintain a constant power supply current, digital switching noise is reduced by 30-300 times compared to conventional CMOS static logic. Measured results are presented for FSCL gates fabricated in a 2-μm CMOS process, and simulated results with a standard 1-μm process are used to compare the power, delay, and switching noise characteristics of FSCL and static logic with 5.0-, 3.3-, and 2.0-V power supplies
Keywords :
CMOS integrated circuits; SPICE; integrated logic circuits; logic gates; mixed analogue-digital integrated circuits; 1 mum; 2 mum; 2 to 5 V; CMOS folded source-coupled logic; CMOS static logic; D-type latch circuits; FSCL inverters; SPICE simulation; constant power supply current; current-steering techniques; digital switching noise reduction; fully-differential FSCL circuits; logic voltage swing; low-noise mixed-signal ICs; power-delay product; ring oscillators; CMOS digital integrated circuits; CMOS logic circuits; Circuit noise; Current supplies; Frequency; Noise reduction; Power capacitors; Power supplies; Switching circuits; Voltage;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
