• DocumentCode
    972293
  • Title

    Low-power gigabit logic by GaAs SSFL

  • Author

    Hashizume, N. ; Yamada, H. ; Kojima, T. ; Matsumoto, K. ; Tomizawa, K.

  • Author_Institution
    Electrical Laboratory, Tsukuba, Japan
  • Volume
    17
  • Issue
    16
  • fYear
    1981
  • Firstpage
    553
  • Lastpage
    554
  • Abstract
    Experimental results on improved GaAs Schottky-barrier coupled Schottky-barrier gate FET logic (SSFL) are reported. A 13-stage ring oscillator, gate dimensions 1.2×20 ¿m2, showed tpd=55 ps/gate at P=3.5 mW/gate. Also, a divide-by-two circuit was confirmed, starting normal operation from a single initialisation pulse.
  • Keywords
    III-V semiconductors; Schottky gate field effect transistors; dividing circuits; field effect integrated circuits; gallium arsenide; integrated logic circuits; GaAs Schottky-barrier coupled Schottky-barrier gate FET logic; III-V semiconductor; SSFL; divide-by-two circuit; low power gigabit logic; ring oscillator;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19810387
  • Filename
    4245862
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=972293