Title :
Improved analog hot-carrier immunity for CMOS mixed-signal applications with LATID technology
Author :
Zhao, Ji ; Chen, Hung-Sheng ; Teng, C.S. ; Moberly, Lawrence
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
fDate :
6/1/1996 12:00:00 AM
Abstract :
This paper reports the results of an investigation of hot-carrier effects on analog performance in LATID (Large-Angle-Tilt-Implanted-Drain) and conventional LDD submicron CMOS technology. The investigation focuses on hot-carrier induced degradation of voltage gain, degradation of drain output resistance, and drift of offset voltage of differential pairs. Results illustrate that LATID technology significantly out-performs LDD technology in regard to hot-carrier immunity of key analog parameters in short channel length devices as well as in relatively long channel length devices. The improvement of analog hot-carrier immunity with LATID is attributed to the mechanisms of reduction and departure of high electrical field from the drain area. Results suggest that LATID technology is a promising candidate for mixed-signal ULSI applications
Keywords :
CMOS integrated circuits; MOSFET; ULSI; hot carriers; ion implantation; mixed analogue-digital integrated circuits; semiconductor device testing; 0.72 to 4.12 mum; 135 angstrom; 5 V; CMOS mixed-signal ULSI; LATID technology; LDD submicron CMOS technology; NMOSFETs; analog hot-carrier immunity; drain output resistance degradation; hot-carrier induced degradation; large-angle-tilt-implanted-drain technology; long channel length devices; offset voltage drift; short channel length devices; voltage gain degradation; Associate members; CMOS technology; Degradation; Hot carrier effects; Hot carriers; Implants; Performance gain; Space technology; Ultra large scale integration; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on