An accurate gate length extraction method for sub-quarter micron MOSFET´s

By comparing measured and simulated gate-to-source/drain capacitances, C_gds, an accurate gate length extraction method is proposed for sub-quarter micron MOSFET´s applications. We show that by including the 2-D field effect on the fringing capacitance, the polysilicon depletion and the quantum-well effects in the C_gds simulation, the polysilicon gate length, L_poly, can be accurately determined for device lengths down to the 0.1 μm regime. The accuracy of this method approaches that of cross-sectional TEM on the device under test, but without destroying the device. Furthermore, we note that as a result of accurate L_poly extraction, the source/drain lateral diffusion length, L_diff , and effective channel length, L_eff, can also be determined precisely. The accuracy of L_diff is confirmed by examining their consistency with experimentally obtained 2-D source/drain profile