Tensile-Strained Germanium CMOS Integration on Silicon

Monolithic integration of tensile-strained Si/ Germanium (Ge)-channel n-MOS and tensile-strained Ge p-MOS with ultrathin (equivalent oxide thickness ~14 Aring) HfO₂ gate dielectric and TaN gate stack on Si substrate is demonstrated. Defect-free Ge layer (279 nm) grown by ultrahigh vacuum chemical-vapor deposition is achieved using a two-step Ge-growth technique coupled with compliant Si/SiGe buffer layers. The epi-Ge layer experiences tensile strain of up to ~0.67% and exhibits a peak hole mobility of 250 cm²/V ldr s which is 100% higher than the universal Si hole mobility. The gate leakage current is two orders of magnitude lower compared to the reported results on Ge bulk.