Title :
Annealing of Si3N4-capped ion-implanted InP
Author :
Gill, Sandeep Singh ; Sealy, B.J. ; Topham, P.J. ; Barrett, N.J. ; Stephens, K.G.
Author_Institution :
University of Surrey, Department of Electronic & Electrical Engineering, Guildford, UK
Abstract :
CVD-Si3N4 layers have been used to encapsulate Se+-implanted InP during annealing in the range 550°C to 730°C. Annealing at 700°C for about 3 min produced the best electrical properties for a dose of 1×1013 Se+ cm¿2, i.e. an electrical activity of 80% and and sheet mobility of 1400 cm2V¿1s¿1.
Keywords :
III-V semiconductors; annealing; indium compounds; ion implantation; selenium; 550degrees C to 730degrees C; CVD-Si3N4 layers; InP:Se+ III-V semiconductor; annealing; electrical activity; sheet mobility;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19810437
