Title :
A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM´s
Author :
Yamauchi, Hiroyuki ; Suzuki, Toshikazu ; Sawada, Akihiro ; Iwata, Tohru ; Tsuji, Toshiaki ; Agata, Masashi ; Taniguchi, Takashi ; Odake, Yoshinori ; Sawada, Kazuyuki ; Ohnishi, Teruhito ; Fukumoto, Masanori ; Fijita, T. ; Inoue, Michihiro
Author_Institution :
Semicond. Res. Lab., Matsushita Electron. Corp., Osaka, Japan
fDate :
11/1/1993 12:00:00 AM
Abstract :
A battery-operated 16-Mb CMOS DRAM with address multiplexing has been developed by using an existing 0.5-μm CMOS technology. It can access data in 36 ns when powered from a 1.8-V battery-source, and 20 ns at 3.3 V. However, this device requires a mere 57 mA of operating current for an 80-ns cycle time and only 5 μA of standby current at 3.3 V. To achieve both high-speed and low-power operation, the following four circuit techniques have been developed: 1) a parallel column access redundancy (PCAR) scheme coupled with a current sensing address comparator (CSAC), 2) an N&PMOS cross-coupled read-bus-amplifier (NPCA), 3) a gate isolated sense amplifier (GISA) with low VT, and 4) a layout that minimizes the length of the signal path by employing the lead on chip (LOC) assembly technique
Keywords :
CMOS integrated circuits; DRAM chips; circuit layout; comparators (circuits); memory architecture; multiplexing; 0.5 mum; 1.8 V; 16 Mbit; 20 ns; 3.3 V; 36 ns; 5 muA; 57 mA; 80 ns; CMOS DRAM; NMOS/PMOS cross-coupled read-bus-amplifier; address multiplexing; circuit technology; current sensing address comparator; cycle time; data access time; gate isolated sense amplifier; high-speed battery-operation; layout; lead on chip assembly technique; low-power operation; operating current; parallel column access redundancy scheme; standby current; Application software; Assembly; CMOS technology; Coupling circuits; High power amplifiers; Lab-on-a-chip; Operational amplifiers; Portable computers; Random access memory; Threshold voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
