A 30-ns 256-Mb DRAM with a multidivided array structure

Author

Sugibayashi, Tadahiko ; Takeshima, Toshio ; Naritake, Isao ; Matano, Tatsuya ; Takada, Hiroshi ; Aimoto, Yoshiharu ; Furuta, Koichiro ; Fujita, Mamoru ; Saeki, Takanori ; Sugawara, Hiroshi ; Murotani, Tatsunori ; Kasai, Naoki ; Shibahara, Kentaro ; Nakaji

Author_Institution

NEC Corp., Sagamihara, Japan

Volume

28

Issue

11

fYear

1993

fDate

11/1/1993 12:00:00 AM

Firstpage

1092

Lastpage

1098

Abstract

A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25-μm CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 μm². Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm²

Keywords

CMOS integrated circuits; DRAM chips; cellular arrays; 0.25 micron; 256 Mbit; 30 ns; 35 mA; 60 ns; CMOS technology; DRAM; HSG cylindrical stacked capacitor cells; I/O width; access time; chip size; cycle time; multidivided array structure; operating current; partial cell array activation scheme; power dissipation; power-line voltage bounce; pull-up data-line architecture; time-sharing refresh scheme; trench isolated cell transistor; Application software; CMOS technology; Capacitors; Circuits; Portable computers; Power dissipation; Random access memory; Time sharing computer systems; Voltage; Wiring;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.245587

Filename

245587