A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM´s

Author

Ukita, Motomu ; Murakami, Shuji ; Yamagata, Tadato ; Kuriyama, Hirotada ; Nishimura, Yasumasa ; Anami, Kenji

Author_Institution

ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan

Volume

28

Issue

11

fYear

1993

fDate

11/1/1993 12:00:00 AM

Firstpage

1114

Lastpage

1118

Abstract

This paper describes a single-bit-line cross-point cell activation (SCPA) architecture, which has been developed to reduce active power consumption and to avoid increase in the size of high-density SRAM chips, such as 16-Mb SRAM´s and beyond. A new PMOS precharging boost circuit, introduced to realize the single-bit-line structure, is also discussed. This circuit is suitable for operation under low-voltage power supply conditions. The SCPA architecture with the new word-line boost circuit is demonstrated with the experimental device, which is fabricated by a 0.4-μm CMOS wafer process technology

Keywords

CMOS integrated circuits; SRAM chips; memory architecture; 0.4 mum; 16 Mbit; CMOS wafer process technology; PMOS precharging boost circuit; SCPA architecture; active power consumption; data sensing scheme; high-density SRAM chips; low-voltage power supply conditions; single-bit-line cross-point cell activation architecture; ultra-low-power SRAM; word-line boost circuit; CMOS memory circuits; CMOS process; CMOS technology; Cities and towns; Decoding; Energy consumption; Memory architecture; Power supplies; Random access memory; SRAM chips;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.245590

Filename

245590