A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier

Author

Seno, Katsunori ; Knorpp, Kurt ; Shu, Lee-Lean ; Teshima, Naoki ; Kihara, Hiroki ; Sato, Hiroshi ; Miyaji, Fumio ; Takeda, Minoru ; Sasaki, Masayoshi ; Tomo, Yoichi ; Chuang, Patrick T. ; Kobayashi, Kazuyoshi

Author_Institution

Semicond. Group, Sony Corp., Kanagawa, Japan

Volume

28

Issue

11

fYear

1993

fDate

11/1/1993 12:00:00 AM

Firstpage

1119

Lastpage

1124

Abstract

A 9-ns 16-Mb CMOS SRAM has been developed using a 0.35-μm CMOS process, The current-mode fully nonequalized data path has been realized in a CMOS SRAM for the first time by using a stabilized feedback current-sense amplifier (SFCA) that provides a small input resistance and an offset compensation effect. To reduce the test time, a bit-line wired-OR parallel test circuit has been implemented

Keywords

CMOS integrated circuits; SRAM chips; integrated circuit testing; 0.35 micron; 16 Mbit; 9 ns; CMOS SRAM; bit-line wired-OR parallel test circuit; fully nonequalized data path; input resistance; offset compensation effect; offset-compensated current sense amplifier; stabilized feedback current-sense amplifier; test time; CMOS process; Circuit testing; Feedback; Large-scale systems; MOS devices; Pulse amplifiers; Pulse circuits; Random access memory; Timing; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.245591

Filename

245591