Title :
A 1.5-ns 32-b CMOS ALU in double pass-transistor logic
Author :
Suzuki, Makoto ; Ohkubo, Norio ; Shinbo, Toshinobu ; Yamanaka, Toshiaki ; Shimizu, Akihiro ; Sasaki, Katsuro ; Nakagome, Yoshinobu
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fDate :
11/1/1993 12:00:00 AM
Abstract :
Describes circuit techniques for fabricating a high-speed adder using pass-transistor logic. Double pass-transistor logic (DPL) is shown to improve circuit performance at reduced supply voltage. Its symmetrical arrangement and double-transmission characteristics improve the gate speed without increasing the input capacitance. A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path. By combining these techniques, the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU. A 32-b ALU test chip is fabricated in 0.25-μm CMOS technology using these circuit techniques and is capable of an addition time of 1.5 ns at a supply voltage of 2.5 V
Keywords :
CMOS integrated circuits; adders; carry logic; integrated logic circuits; 0.25 micron; 1.5 ns; 2.5 V; 32 bit; CMOS ALU; addition time; carry propagation circuit technique; conditional carry selection; double pass-transistor logic; double-transmission characteristics; gate speed; high-speed adder; reduced supply voltage; Adders; CMOS logic circuits; CMOS technology; Capacitance; Carbon capture and storage; Circuit optimization; Circuit testing; Logic circuits; Page description languages; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
