Computing lower bounds on functional units before scheduling

Author

Chaudhuri, Samit ; Walker, Robert A.

Author_Institution

Cadence Design Syst. Inc., Chelmsford, MA, USA

Volume

4

Issue

2

fYear

1996

fDate

6/1/1996 12:00:00 AM

Firstpage

273

Lastpage

279

Abstract

The authors present a new polynomial-time algorithm for computing lower bounds on the number of functional units (FUs) of each type required to schedule a data flow graph in a specified number of control steps. A formal approach is presented that is guaranteed to find the tightest possible bounds that can be found by relaxing either the precedence constraints or integrality constraints on the scheduling problem. This tight, yet fairly efficient, bounding method can be used to estimate FU area, to generate resource constraints for reducing the search space, or in conjunction with exact techniques for efficient optimal design space exploration.

Keywords

VLSI; circuit CAD; data flow graphs; formal specification; high level synthesis; integrated circuit design; scheduling; VLSI synthesis; data flow graph scheduling; functional units; lower bounds; optimal design space exploration; polynomial-time algorithm; resource constraints; Data flow computing; Flow graphs; High level synthesis; Polynomials; Processor scheduling; Scheduling algorithm; Space exploration; Systems engineering and theory; Upper bound; Very large scale integration;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.502199

Filename

502199