Title :
Automatic synthesis of dynamically configured pipelines supporting variable data initiation intervals
Author :
Jun, Hong-Shin ; Hwang, Sun-Young
Author_Institution :
Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea
fDate :
6/1/1996 12:00:00 AM
Abstract :
The authors propose a new approach for synthesizing the dynamically configured pipelines supporting variable data initiation intervals (DIIs). Compared to the previous research where the pipeline synthesis is confined to those with fixed DIIs, the proposed system allows powerful design space exploration by removing the constraints of fixed DIIs. The proposed algorithm tries to optimize the area of pipeline structures by fully utilizing hardware resources to which abstract operations in high-level design descriptions are assigned, while meeting the given timing constraints in the clock cycle time, number of stages, and data initiation sequence. Experimental results on benchmarks show that new design points, efficient in speed and in area, can be found by removing the restriction of fixed DIIs in the synthesis of pipeline structures.
Keywords :
VLSI; circuit CAD; circuit optimisation; high level synthesis; integrated circuit design; pipeline processing; timing; automatic synthesis; clock cycle time; design space exploration; dynamically configured pipelines; high-level design descriptions; pipeline synthesis; timing constraints; variable data initiation intervals; Central Processing Unit; Circuits; Design automation; Flow graphs; IEEE Computer Society Press; Optimal scheduling; Pipelines; Polynomials; Processor scheduling;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on