DocumentCode :
973405
Title :
A 56 mW Continuous-Time Quadrature Cascaded Σ∆ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band
Author :
Breems, Lucien J. ; Rutten, Robert ; van Veldhoven, Robert H.M. ; van der Weide, Gerard
Author_Institution :
NXP Semicond. Res., Eindhoven
Volume :
42
Issue :
12
fYear :
2007
Firstpage :
2696
Lastpage :
2705
Abstract :
A quadrature cascaded modulator with continuous-time loop filters is presented for a digital multi-stream FM radio receiver. The ADC achieves a dynamic range of 77 dB and 20 MHz bandwidth centered on an intermediate frequency of 10.5 MHz and is sampling at 340 MHz. The cascaded modulator comprises programmable analog second-order quadrature filters and a digital quadrature noise cancellation filter. The 0.5 chip in 90 nm CMOS consumes 56 mW from a 1.2 V supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; continuous time filters; frequency modulation; quadrature amplitude modulation; radio receivers; bandwidth 20 MHz; cascaded modulator; continuous-time loop filters; continuous-time quadrature SigmaDelta modulator; digital multistream FM radio receiver; digital quadrature noise cancellation filter; frequency 10.5 MHz; frequency 340 MHz; noise figure 77 dB; power 56 mW; programmable analog second-order quadrature filters; size 90 nm; voltage 1.2 V; Bandwidth; Delta-sigma modulation; Digital filters; Digital modulation; Digital signal processing; Dynamic range; Frequency modulation; Noise cancellation; Receivers; Tuners; ADC; FM radio; MASH; analog-to-digital conversion; calibration; cascaded; complex; continuous-time; multi-bit; multi-stream; noise cancellation; quadrature; sigma-delta modulation;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2007.908765
Filename :
4381437
Link To Document :
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