Title :
A 40–44 Gb/s 3× Oversampling CMOS CDR/1:16 DEMUX
Author :
Nedovic, Nikola ; Tzartzanis, Nestoras ; Tamura, Hirotaka ; Rotella, Francis M. ; Wiklund, Magnus ; Mizutani, Yuma ; Okaniwa, Yusuke ; Kuroda, Tadahiro ; Ogawa, Junji ; Walker, William W.
Author_Institution :
Fujitsu Lab. of America, Sunnyvale
Abstract :
A CMOS CDR and 1:16 DEMUX fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3times blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER <10-12 with a 231-1 PRBS source) is demonstrated using both an on-chip and an external BERT.
Keywords :
CMOS integrated circuits; error statistics; synchronisation; voltage-controlled oscillators; BER; VCO; blind-oversampling architecture; clock and data recovery unit; frequency 2.5 GHz; frequency acquisition; mask tolerance; oversampling CMOS DEMUX; quarter-rate hybrid phase-tracking; CMOS technology; Circuits; Clocks; Consumer electronics; Energy consumption; Germanium silicon alloys; Indium phosphide; Jitter; Laboratories; Silicon germanium; CML; CMOS; Clock and data recovery (CDR); delay line; demultiplexer; distributed VCO; distributed circuits; hybrid CDR; jitter tolerance; optical communications; oversampling; serializer-deserializer;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2007.908714
