Title :
Heterodyne Phase Locking: A Technique for High-Speed Frequency Division
Author_Institution :
Univ. of California, Los Angeles
Abstract :
A phase-locked loop incorporating a cascade of mixers can provide integer or fractional divide ratios at high frequencies. The circuit topology and its variants are presented, and their advantages over static, dynamic, and injection-locked dividers are described. The effect of nonidealities such as the spurious response and noise of the mixers is also analyzed. A divide-by-two prototype realized in 0.13-mum CMOS technology operates from 64 GHz to 70 GHz while consuming 6 mW from a 1.2-V supply.
Keywords :
CMOS integrated circuits; network topology; phase locked loops; CMOS technology; circuit topology; frequency 64 GHz to 70 GHz; heterodyne phase locking; high-speed frequency division; injection-locked dividers; mixers; phase-locked loop; power 6 mW; size 0.13 mum; voltage 1.2 V; CMOS technology; Circuit topology; Frequency conversion; Inductors; Injection-locked oscillators; Millimeter wave circuits; Phase locked loops; Phase noise; Prototypes; Synthesizers; LC oscillators; Frequency synthesizers; Miller dividers flip flops; injection locking; lock range; millimeter-wave dividers;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2007.908742
