Title :
Efficient algorithm for FPGA board routing
Author :
Song, X. ; Dharmadhikari, M. ; Mohamed, O. Ait ; Chrzanowska-Jeske, M.
Author_Institution :
Dept. of ECE, Portland State Univ., OR, USA
fDate :
4/15/2004 12:00:00 AM
Abstract :
A simple and fast algorithm for solving the two-terminal board level routing problem in FPGA-based logic emulation systems is presented. The method is based on the net scan selection process. Experimental results are the first implemented results for an algorithm presented previously. The comparison results show that the current approach achieves better effectiveness and uses less CPU time.
Keywords :
field programmable gate arrays; network routing; optimisation; FPGA based logic emulation system; FPGA board routing; heuristic algorithm; net scan selection process; two terminal board level routing problem;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20040277
