Title :
VLSI implementation of synaptic weighting and summing in pulse coded neural-type cells
Author :
Moon, Gyu ; Zaghloul, Mona E. ; Newcomb, Robert W.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., George Washington Univ., DC, USA
fDate :
5/1/1992 12:00:00 AM
Abstract :
Presents the hardware realization for synaptic weighting and summing using pulse-coded neural-type cells (NTCs). The basic information processing element (NTC) encodes the information into the form of pulse duty cycles using voltage-controlled resistors, for which a pulse duty cycle modulation technique is proposed. Summation is executed by a simple capacitor circuit as a current integrator. Layouts and measurements on a fabricated integrated design are included
Keywords :
VLSI; integrating circuits; neural nets; VLSI implementation; capacitor circuit; current integrator; information processing element; pulse coded neural-type cells; pulse duty cycles; synaptic summing; synaptic weighting; voltage-controlled resistors; Biological information theory; Capacitors; Moon; Neural network hardware; Neurons; Pulse circuits; Pulse modulation; Resistors; Very large scale integration; Voltage;
Journal_Title :
Neural Networks, IEEE Transactions on
