A modular CMOS design of a Hamming network

Author

Robinson, Moisés E. ; Yoneda, Hideki ; Sánchez-Sinencio, Edgar

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

Volume

3

Issue

3

fYear

1992

fDate

5/1/1992 12:00:00 AM

Firstpage

444

Lastpage

456

Abstract

A modular design approach for the CMOS implementation of a Hamming network is proposed. The Hamming network is an optimum minimum error classifier for binary patterns and is very suitable for a VLSI implementation due to its primarily feedforward structure. First, a modular chip that contains an array of N×M exclusive-NOR transconductors computes the matching scores between M encoded exemplar patterns (with N elements per exemplar) and an unknown input pattern. Then, a winner-take-all (WTA) circuit selects the exemplar pattern that most resembles the input pattern. By interconnecting multiple modular chips, the number and size of the patterns that can be stored in the network can be easily expanded. Measured experimental results are given to illustrate the performance and limitations of the hardware implementations of the Hamming network

Keywords

CMOS integrated circuits; VLSI; neural nets; pattern recognition; Hamming network; VLSI implementation; binary patterns; exemplar patterns; feedforward structure; matching scores; modular CMOS design; multiple modular chips; neural nets; optimum minimum error classifier; transconductors; unknown input pattern; Computer networks; Helium; Integrated circuit interconnections; Neural networks; Pattern matching; Pattern recognition; Semiconductor device measurement; Training data; Transconductors; Very large scale integration;

fLanguage

English

Journal_Title

Neural Networks, IEEE Transactions on

Publisher

ieee

ISSN

1045-9227

Type

jour

DOI

10.1109/72.129417

Filename

129417