Analog CMOS implementation of a multilayer perceptron with nonlinear synapses

Author

Lont, Jerzy B. ; Guggenbühl, Walter

Author_Institution

Electron. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland

Volume

3

Issue

3

fYear

1992

fDate

5/1/1992 12:00:00 AM

Firstpage

457

Lastpage

465

Abstract

A neurocomputer based on a high-density analog integrated circuit developed in a 3 μm CMOS technology has been built. The 1.6 mm×2.4 mm chip contains 18 neurons and 161 synapses in three layers, and provides 16 inputs and 4 outputs. The weights are stored on storage capacitors of the synapses. A formalization of the error back-propagation algorithm which allows the use of very small nonlinear synapses is shown. The influence of offset voltages in the synapses on the circuit performance is analyzed. Some experimental results are reported and discussed

Keywords

CMOS integrated circuits; analogue circuits; neural nets; 3 micron; CMOS technology; circuit performance; error back-propagation algorithm; high-density analog integrated circuit; multilayer perceptron; neurocomputer; nonlinear synapses; offset voltages; storage capacitors; Analog integrated circuits; CMOS analog integrated circuits; CMOS technology; Capacitors; Circuit analysis; Circuit optimization; Integrated circuit technology; Multilayer perceptrons; Neurons; Voltage;

fLanguage

English

Journal_Title

Neural Networks, IEEE Transactions on

Publisher

ieee

ISSN

1045-9227

Type

jour

DOI

10.1109/72.129418

Filename

129418