DocumentCode :
974494
Title :
A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II: Implementation and Implications for Power Estimation and Thermal Management
Author :
Lin, Sheng-Chih ; Chrysler, Greg ; Mahajan, Ravi ; De, Vivek K. ; Banerjee, Kaustav
Author_Institution :
Univ. of California, Santa Barbara
Volume :
54
Issue :
12
fYear :
2007
Firstpage :
3351
Lastpage :
3360
Abstract :
As transistors continue to evolve along Moore´s Law and silicon devices take advantage of this evolution to offer increasing performance, there is a critical need to accurately estimate the silicon-substrate (junction or die) thermal gradients and temperature profile for the development and thermal management of future generations of all high-performance integrated circuits (ICs) including microprocessors. This paper presents an accurate chip-level leakage-aware method that self-consistently incorporates various electrothermal couplings between chip power, junction temperature, operating frequency, and supply voltage for substrate thermal profile estimation and also employs a realistic package thermal model that comprehends different packaging layers and noncubic structure of the package, which are not accounted for in traditional analyses. The evaluation using the proposed methodology is efficient and shows excellent agreements with an industrial-quality computational-fluid-dynamics (CFD) based commercial software. Furthermore, the methodology is shown to become increasingly effective with increase in leakage as technology scales. It is shown that considering electrothermal couplings and realistic package thermal model not only improves the accuracy of estimating the heat distribution across the chip but also has significant implications for precise power estimation and thermal management in nanometer-scale CMOS technologies.
Keywords :
CMOS integrated circuits; chip scale packaging; integrated circuit modelling; nanoelectronics; substrates; thermal management (packaging); chip-level leakage-aware method; electrothermal couplings; heat distribution; high-performance integrated circuits; junction temperature; nanometer-scale CMOS technologies; noncubic structure; power estimation; realistic package thermal model; self-consistent substrate thermal profile estimation; silicon-substrate thermal gradients; temperature profile; thermal management; CMOS technology; Electrothermal effects; Energy management; Frequency estimation; Integrated circuit packaging; Moore´s Law; Silicon devices; Temperature; Thermal management; Transistors; Integrated circuits; leakage; performance; power; temperature gradient; thermal management;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2007.909038
Filename :
4383040
Link To Document :
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