IIR double-sampled switched-capacitor decimators for high-frequency applications

Author

Baschirotto, A. ; Castello, R. ; Montecchi, F.

Author_Institution

Dipartimento di Elettronica, Pavia Univ., Italy

Volume

39

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

300

Lastpage

304

Abstract

The possibility of implementing the double-sampling (DS) techinque in infinite impulse response (IIR) first- and second-order switched-capacitor (SC) decimators is considered. The DS-SC circuits that result are designed using the same procedure as standard IIR decimators, and only a different SC implementation results with a reorganized clock phasing. The main advantage is that the time allowed for the op-amps to settle can be equal to the output sampling period rather than one half of it. Using the proposed DS decimators allows the design of high-frequency SC filtering systems (an antialiasing SC decimator filter and a `core´ DS-SC filter) where the op-amp speed requirements are the same in each block

Keywords

active filters; active networks; switched capacitor filters; switched capacitor networks; IIR decimators; SC filtering systems; SC implementation; antialiasing filter; clock phasing; double-sampling; first-order type; high-frequency applications; infinite impulse response; op-amps; second-order; switched-capacitor decimators; Artificial intelligence; Circuits; Clocks; Operational amplifiers; Polynomials; Sampling methods;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.129459

Filename

129459