Flexible VLSI architecture of motion estimator for video image compression

Author

Nam, Seung Hyun ; Lee, Moon Key

Author_Institution

Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea

Volume

43

Issue

6

fYear

1996

fDate

6/1/1996 12:00:00 AM

Firstpage

467

Lastpage

470

Abstract

A linear array architecture for a full-search block matching algorithm is proposed. It is suitable for low bit-rate video applications with a single chip realization. It uses a parallel algorithm based on the idea of partial result accumulation. Combining a serial data input with registers for a line of search window pixels and operating on them in parallel, the partial results of the candidate block distortions are obtained for all horizontal search positions, which are successively accumulated into a cyclic storage buffer. Based on this scheme, a flexible architecture can be designed for motion vector estimation of different search ranges and block sizes

Keywords

VLSI; buffer storage; data compression; digital signal processing chips; image matching; image processing equipment; motion estimation; parallel algorithms; parallel architectures; performance evaluation; pipeline processing; video coding; DSP chip; candidate block distortions; cyclic storage buffer; flexible VLSI architecture; full-search block matching algorithm; linear array architecture; low bit-rate video applications; motion estimator; motion vector estimation; parallel algorithm; partial result accumulation; search window pixels; serial data input; single chip realization; video image compression; Broadcasting; Buffer storage; Clocks; Image coding; Moon; Motion estimation; Parallel algorithms; Registers; Very large scale integration; Video compression;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.502319

Filename

502319