DocumentCode :
974682
Title :
Design of a DPCM codec for VLSI realization in CMOS technology
Author :
Pirsch, Peter
Author_Institution :
Standard Elektrik Lorenz AG, Stuttgart, Federal Republic of Germany
Volume :
73
Issue :
4
fYear :
1985
fDate :
4/1/1985 12:00:00 AM
Firstpage :
592
Lastpage :
598
Abstract :
Current perspectives on broad-band communication services have made the realization of a DPCM system for video coding on a single integrated circuit particularly important. A nonadaptive intraframe DPCM system is designed for reducing video transmission bit rate by a factor of two. All functional blocks of a DPCM codec have been specified, and modifications have been investigated for reducing speed requirements. Alternative realizations of functional blocks, e.g., adders, subtractors, table look-up operations, are compared with respect to speed by a simple delay model. A one-chip VLSI implementation of an efficient DPCM codec will be possible with a 2-µm CMOS technology.
Keywords :
Adders; Bit rate; Broadband communication; CMOS technology; Codecs; Delay; Integrated circuit technology; Semiconductor device modeling; Very large scale integration; Video coding;
fLanguage :
English
Journal_Title :
Proceedings of the IEEE
Publisher :
ieee
ISSN :
0018-9219
Type :
jour
DOI :
10.1109/PROC.1985.13186
Filename :
1457454
Link To Document :
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