• DocumentCode
    975949
  • Title

    Cortical Models Onto CMOL and CMOS— Architectures and Performance/Price

  • Author

    Gao, Changjian ; Hammerstrom, Dan

  • Author_Institution
    Portland State Univ., Portland
  • Volume
    54
  • Issue
    11
  • fYear
    2007
  • Firstpage
    2502
  • Lastpage
    2515
  • Abstract
    Here we introduce a highly simplified model of the neocortex based on spiking neurons, and then investigate various mappings of this model to the CMOL CrossNet nanogrid nanoarchitecture. The performance/price is estimated for several architectural configurations both with and without nanoscale circuits. In this analysis we explore the time multiplexing of computational hardware for a pulse-based variation of the model. Our analysis demonstrates that the mixed-signal CMOL implementation has the best performance/price in both nonspiking and spiking neural models. However, these circuits also have serious power density issues when interfacing the nanowire crossbars to analog CMOS circuits. Although the results presented here are based on biologically based computation, the use of pulse-based data representation for nanoscale circuits has much potential as a general architectural technique for a range of nanocircuit implementation.
  • Keywords
    CMOS integrated circuits; integrated circuit design; integrated circuit modelling; nanoelectronics; neural nets; CMOL CrossNet nanogrid nanoarchitecture; analog CMOS circuits; architectural configurations; computational hardware; cortical models; hierarchical distributed memory; mixed-signal CMOL implementation; multiplexing circuit design; nanoelectronics; nanoscale circuits; nanowire crossbars; neocortex; nonspiking neural model; pulse-based data representation; pulse-based variation; spiking neurons; time multiplexing; Biological system modeling; Biology computing; CMOS analog integrated circuits; Circuit analysis; Hardware; Nanobioscience; Neurons; Performance analysis; Pulse circuits; Semiconductor device modeling; Architecture performance and price; hierarchical distributed memory (HDM); multiplexing circuit design; nanoelectronics;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-8328
  • Type

    jour

  • DOI
    10.1109/TCSI.2007.907830
  • Filename
    4383243