Title :
An experimental 1-Mbit cache DRAM with ECC
Author :
Asakura, Mikio ; Matsuda, Yoshio ; Hidaka, Hideto ; Tanaka, Yoshinori ; Fujishima, Kazuyasu
Author_Institution :
Mitsubishi Electr. Corp., Itami, Japan
fDate :
2/1/1990 12:00:00 AM
Abstract :
A cache DRAM which consists of a dynamic RAM (DRAM) as main memory and a static RAM (SRAM) as cache memory is proposed. An error checking and correcting (ECC) scheme utilizing the wide internal data bus is also proposed. It is constructed to be suitable for a four-way set associated cache scheme with more than a 90% hit rate estimated to be obtained. An experimental cache DRAM with 1-Mb DRAM and 8-kb SRAM has been fabricated using a 1.2-μm, triple-polysilicon, single-metal CMOS process. A SRAM access time of 12 ns and a DRAM access time of 80 ns, including an ECC time of 12 ns, have been obtained. Accordingly, an average access time of 20 ns is expected under the condition that the hit rate is 90%. The cache DRAM has a high-speed data mapping capability and high reliability suitable for low-end workstations and personal computers
Keywords :
CMOS integrated circuits; VLSI; buffer storage; error correction; integrated circuit technology; integrated memory circuits; random-access storage; 1 Mbit; 1.2 micron; 12 ns; 8 kbit; 80 ns; DRAM; DRAM access time; ECC; ECC time; SRAM; SRAM access time; average access time; cache DRAM; cache memory; dynamic RAM; error checking and correcting scheme; four-way set associated cache scheme; high reliability; high-speed data mapping capability; hit rate; low-end workstations; personal computers; polycrystalline Si; single-metal CMOS process; static RAM; triple-polysilicon; wide internal data bus; CMOS process; CMOS technology; Cache memory; DRAM chips; Delay effects; Error correction; Error correction codes; Microcomputers; Random access memory; Read-write memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
