A circuit design to suppress asymmetrical characteristics in high-density DRAM sense amplifiers

Author

Yamauchi, Hiroyuki ; Yabu, Toshiki ; Yamada, Toshio ; Inoue, Michihiro

Author_Institution

Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

Volume

25

Issue

1

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

36

Lastpage

41

Abstract

A circuit design technique for suppressing asymmetrical characteristics in a high-density DRAM sense amplifier is discussed, and the effect of drain current imbalances between transistor pairs and the sensitivity of the sense amplifier are studied experimentally. A sense amplifier composed of parallel transistor pairs which have a reversed source and drain arrangement on a wafer is capable of suppressing the asymmetry effects to less than 15 mV in a range of submicrometer gate lengths and of reducing the layout area by about 43% compared with the conventional sense amplifier

Keywords

CMOS integrated circuits; VLSI; amplifiers; integrated circuit technology; integrated memory circuits; random-access storage; 15 mV; CMOS; ULSI; circuit design technique; drain current imbalances; high-density DRAM sense amplifiers; layout area reduction; multi megabit memories; parallel transistor pairs; reversed source and drain arrangement; submicrometer gate lengths; suppressing asymmetrical characteristics; CMOS technology; Capacitance; Circuit synthesis; Degradation; Electrodes; Equivalent circuits; Ion implantation; MOSFET circuits; Random access memory; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.50281

Filename

50281