DocumentCode
976613
Title
Systolic random number generation for genetic algorithms
Author
Bland, I.M. ; Megson, G.M.
Author_Institution
Dept. of Comput. Sci., Reading Univ., UK
Volume
32
Issue
12
fYear
1996
fDate
6/6/1996 12:00:00 AM
Firstpage
1069
Lastpage
1070
Abstract
A parallel hardware random number generator for use with a VLSI genetic algorithm (GA) processing device is proposed. The design uses a systolic array of mixed congruential random number generators. The generators are constantly reseeded with the outputs of the proceeding generators to avoid significant biasing of the randomness of the array, which would result in longer times for the algorithm to converge to a solution
Keywords
VLSI; genetic algorithms; random number generation; systolic arrays; VLSI processing device; genetic algorithm; parallel hardware; random number generator; systolic array;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19960709
Filename
502856
Link To Document