Title :
Integrated tapped MOS analogue delay line using switched capacitor technique
Author :
Enomoto, Tetsuya ; Ishihara, Takuya ; Yasumoto, Masa-Aki
Author_Institution :
Nippon Electric Co. Ltd., Basic Technology Research Laboratories, Kawasaki, Japan
Abstract :
A tapped MOS analogue delay line based on the switched capacitor technique for realisation of low-power analogue LSIs is fabricated using a VLSI process. Excellent characteristics such as large signal handling capability, low total harmonic distortion of ¿85 dB for 3V(p-p) input and fast operation speed of more than 1 MHz clock rate with negligible charge transfer loss are obtained.
Keywords :
delay lines; field effect integrated circuits; large scale integration; switched capacitor networks; 1 MHz clock rate; VLSI process; charge transfer loss; harmonic distortion; integrated tapped MOS analogue delay line; low-power analogue LSIs; switched capacitor technique;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19820133
