Title :
A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design
Author :
Imamiya, Kenichi ; Miyamoto, Junichi ; Atsumi, Shigeru ; Ohtsuka, Nobuaki ; Muroya, Yukinori ; Sako, Toshiyuki ; Higashino, Masao ; Iyama, Yumiko ; Mori, Seiichi ; Ohshima, Yoichi ; Araki, Hitoshi ; Kaneko, Yukio ; Narita, Kazuhito ; Arai, Norihisa ; Yosh
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fDate :
2/1/1990 12:00:00 AM
Abstract :
In a VLSI memory, noise generated by its own operation is a serious problem. The noise disturbs data sensing, especially in EPROMs which have a single-ended sensing scheme. To develop high-density and high-speed EPROMs, it is necessary to solve the noise problems. Incorrect EPROM functions due to the noise are discussed. High-noise-immunity circuit techniques for stable data sensing and high-speed access time are proposed. These are divided bit-line layout, reference line with dummy bit lines, and a chip-enable transition detector. Using these circuit techniques and 0.8-μm n-well CMOS technology, a 512 K×8-b CMOS EPROM was developed. A 68-ns access time was achieved. The die size is 5.62 mm×15.30 mm, and it is assembled in a 600-mil cerdip package
Keywords :
CMOS integrated circuits; EPROM; VLSI; integrated circuit technology; integrated memory circuits; 0.8 micron; 4 Mbit; 5.62 to 15.3 mm; 512 kbyte; 600 mil; 68 ns; CMOS EPROM; ULSI; VLSI memory; cerdip package; chip-enable transition detector; circuit techniques; die size; divided bit-line layout; high noise immunity circuit techniques; high-noise-immunity design; high-speed EPROMs; high-speed access time; megabit EPROM; n-well CMOS technology; reference line with dummy bit lines; single-ended sensing scheme; stable data sensing; submicron; CMOS technology; Circuit noise; EPROM; Noise generators; Noise level; Packaging; Parasitic capacitance; Semiconductor device noise; Very large scale integration; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
