A 100-mega-access per second matching memory for a data-driven microprocessor

Author

Takata, Hidehiro ; Komori, Shinji ; Tamura, Toshiyuki ; Asai, Fumiyasu ; Satoh, Hisakazu ; Ohno, Takio ; Tokuda, Takeshi ; Nishikawa, Hiroaki ; Terada, Hiroaki

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

Volume

25

Issue

1

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

95

Lastpage

99

Abstract

A high-throughput matching memory (MM) for a data-driven microprocessor is discussed. An MM can be constructed using a hashing memory. However, one of the biggest problems with hashing memory is the necessity for selective processing whenever hashed address conflicts occur. To eliminate this problem, the MM incorporated a small amount of associative memory (32 words×50 b) as well as the hashing memory (512 words×42 b). The matching operation is subdivided into three pipeline stages, all controlled by the elastic pipeline scheme. With this structure, an MM with a high throughput of 100-mega-access/s MM can be realized

Keywords

CMOS integrated circuits; VLSI; content-addressable storage; integrated circuit technology; integrated memory circuits; random-access storage; 100 MHz; 100-mega-access per second matching memory; 1600 bit; 21504 bit; 42 bit; 50 bit; associative memory; data-driven microprocessor; elastic pipeline scheme; hashing memory; high-throughput matching memory; matching operation; pipeline stages; Associative memory; Circuits; Laboratories; Large scale integration; Latches; Microprocessors; Parallel processing; Pipelines; Research and development; Throughput;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.50290

Filename

50290