Title :
Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode
Author :
Shiyang Zhu ; Yu, H.Y. ; Whang, S.J. ; Chen, J.H. ; Chen Shen ; Chunxiang Zhu ; Lee, S.J. ; Li, M.F. ; Chan, D.S.H. ; Yoo, W.J. ; Du, A. ; Tung, C.H. ; Singh, Jaskirat ; Chin, Alvin ; Kwong, D.L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore
fDate :
5/1/2004 12:00:00 AM
Abstract :
This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-κ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of Ion/Ioff∼107-108 and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi2-x S/D , Ion/Ioff can reach ∼105 at Vds of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-κ dielectric and metal-gate materials to be used in the future generation CMOS technology.
Keywords :
MOSFET; Schottky barriers; semiconductor device manufacture; CMOS technology; DySi; MOSFET; PtSi; Schottky barrier; electrical performance; high-κ dielectric material; low-temperature process; metal-gate material; semiconductor device fabrication; silicide source-drain transistors; subthreshold slope; thermal budget; Annealing; CMOS technology; Dielectrics; Electrodes; Hafnium oxide; Laboratories; MOSFETs; Microelectronics; Silicides; Silicon;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2004.826569
