A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC

Author

Nogami, Kazutaka ; Sakurai, Takayasu ; Sawada, Kazuhiro ; Sakaue, Kenji ; Miyazawa, Yuichi ; Tanaka, Shigeru ; Hiruta, Yoichi ; Katoh, Katsuto ; Takayanagi, Toshinari ; Shirotori, Tsukasa ; Itoh, Yukiko ; Uchida, Masanori ; Iizuka, Tetsuya

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

25

Issue

1

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

100

Lastpage

108

Abstract

A 32-kB cache macro with an experimental reduced instruction set computer (RISC) is realized. A pipelined cache access to realize a cycle time shorter than the cache access time is proposed. A double-word-line architecture combines single-port cells, dual-port cells, and CAM cells into a memory array to improve silicon area efficiency. The cache macro exhibits 9-ns typical clock-to-HIT delay as a result of several circuit techniques, such as a section word-line selector, a dual transfer gate, and 1.0-μm CMOS technology. It supports multitask operation with logical addressing by a selective clear circuit. The RISC includes a double-word load/store instruction using a 64-b bus to fully utilize the on-chip cache macro. A test scheme allows measurement of the internal signal delay. The test device design is based on the unified design rules scalable through multigenerations of process technologies down to 0.8 μm

Keywords

CMOS integrated circuits; VLSI; buffer storage; content-addressable storage; integrated memory circuits; random-access storage; reduced instruction set computing; 1 to 0.8 micron; 32 kbyte; 64 bit; 9 ns; CAM cells; CMOS technology; HIT-delay; SRAM cell; cache access time; circuit techniques; clock-to-HIT delay; cycle time; double-word-line architecture; dual transfer gate; dual-port cells; high-speed RISC; logical addressing; memory array; multitask operation; on-chip cache macro; pipelined cache access; process technologies; reduced instruction set computer; scalable; section word-line selector; selective clear circuit; single-port cells; test scheme; unified design rules; CADCAM; CMOS technology; Circuit testing; Clocks; Computer aided instruction; Computer aided manufacturing; Computer architecture; Delay; Reduced instruction set computing; Silicon;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.50291

Filename

50291