Title :
8.5 mΩ · cm2 600-V double-epitaxial MOSFETs in 4H-SiC
Author :
Harada, Shinsuke ; Okamoto, Mitsuo ; Yatsuo, Tsutomu ; Adachi, Kazuhiro ; Fukuda, Kenji ; Arai, Kazuo
Author_Institution :
Power Electron. Res. Center, Nat. Inst. of Adv. Ind. Sci. & Technol., Tsukuba, Japan
fDate :
5/1/2004 12:00:00 AM
Abstract :
The most important issue in realizing a 4H-SiC vertical MOSFET is to improve the poor channel mobility at the MOS interface, which is related to high on-resistance. This letter focuses on a novel 4H-SiC vertical MOSFET device structure where a low acceptor concentration epitaxial layer is used as a channel. We call this structure a double-epitaxial MOSFET (DEMOSFET). In the structure, the p-well is composed of two p-type epitaxial layers, while an n-type region between the p-wells is formed by low-dose n-type ion implantation. A buried channel is formed at the surface of the upper p$epitaxial layer. A fabricated DEMOSFET showed an on-resistance of 8.5 mΩ·cm2 at a gate voltage of 15 V and a blocking voltage of 600 V. This on-resistance is the lowest so far reported for a vertical MOSFET with a blocking voltage of 600 V.
Keywords :
MOSFET; doping profiles; ion implantation; semiconductor device manufacture; semiconductor epitaxial layers; silicon compounds; wide band gap semiconductors; 15 V; 600 V; MOS interface; SiC; blocking voltage; channel mobility; device structure; double-epitaxial MOSFET; epitaxial layer; gate voltage; low acceptor concentration; low-dose n-type ion implantation; n-type region; on-resistance; p-type epitaxial layers; p-well; vertical MOSFET; Electric breakdown; Electron mobility; Epitaxial layers; Helium; Ion implantation; MOSFETs; Rough surfaces; Silicon carbide; Surface roughness; Voltage;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2004.826538
