DocumentCode
977597
Title
1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture
Author
Kuo, J.B. ; Su, K.W. ; Lou, J.H.
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
29
Issue
24
fYear
1993
Firstpage
2097
Lastpage
2098
Abstract
A 1.5V BiCMOS dynamic multiplier is presented which is free from race and charge sharing problems, using Wallace tree reduction architecture and a 1.5V full-swing BiCMOS dynamic logic circuit. Based on a 1 mu m BiCMOS technology, a designed 1.5V 8*8 multiplier shows a *2.3 improvement in speed as compared to the CMOS static multiplier.
Keywords
BiCMOS integrated circuits; digital arithmetic; integrated logic circuits; multiplying circuits; 1.5 V; 8*8 multiplier; BiCMOS dynamic logic circuit; BiCMOS dynamic multiplier; Wallace tree reduction architecture;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19931402
Filename
247592
Link To Document