Title :
n+/p+ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors
Author :
Jung, Han-A-Reum ; Park, Ki-Heung ; Lee, Jong-Ho
Author_Institution :
Kyungpook Nat. Univ., Daegu
Abstract :
We proposed a new p+/n+ poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p+ polygate. Key device characteristics were investigated by changing the n+ poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length Lg. It was shown that the trench filled with p+ poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent Ion/Ioff (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width Wcfin at given Lg ´s of 30, 40, and 50 nm.
Keywords :
DRAM chips; MOSFET; nanoelectronics; semiconductor device testing; silicon; DRAM cell transistors; Si - Interface; device characteristics; dynamic random access memory cell transistors; gate bulk FinFET; locally separated channel structure; poly-silicon gate bulk fin-type field-effect transistor; size 30 nm; size 40 nm; size 50 nm; source-drain diffusion region; Business; DRAM chips; Electronic mail; Etching; FETs; Filling; FinFETs; Nonvolatile memory; Random access memory; Threshold voltage; $hbox{n}^{+}/hbox{p}^{+}$ gate; Channel separation; dynamic random access memory (DRAM); fin-type field-effect transistor (FinFET); gate-induced drain leakage (GIDL); sub-50 nm;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2007.909870
