Effect of a Two-Step Recess Process Using Atomic Layer Etching on the Performance of In0.52Al0.48As/In0.53Ga0.47As p-HEMTs

The characteristics of 0.15- mum InAlAs/InGaAs pseudomorphic high-electron mobility transistors (p-HEMTs) that were fabricated using the Ne-based atomic layer etching (ALET) technology and the Ar-based conventional reactive ion etching (RIE) technology were investigated. As compared with the RIE, the ALET used a much lower plasma energy and thus produced much lower plasma-induced damages to the surface and bulk of the In_0.52AI_0.48As barrier and showed a much higher etch selectivity (~70) of the InP spacer against the In_0.52Al_0.48As barrier. The 0.15-mum InAlAs/InGaAs p-HEMTs that were fabricated using the ALET exhibited improved G_m,max (1.38 S/mm), I_ONn/I_OFF(1.18X10⁴), drain-induced barrier lowering (80 mWV), threshold voltage uniformity (V_th,avg = -190 mV and alpha = 15 mV), and ftau (233 GHz), mainly due to the extremely low plasma-induced damage in the Schottky gate area.