DocumentCode
978709
Title
Efficient hardware optimisation algorithm for fixed point digital signal processing ASIC design
Author
Hwang, Sun-Young
Volume
32
Issue
11
fYear
1996
fDate
5/23/1996 12:00:00 AM
Firstpage
992
Lastpage
994
Abstract
The authors present a novel algorithm for area minimisation in digital signal processing ASIC design. After determining the optimised fixed point representation for each signal, the proposed algorithm divides abstract operations in design description into partitions so that operations in the same partition can share a hardware module. Experimental results show the efficacy of the proposed algorithm by generating the DSP hardwares requiring smaller area under given performance constraints
Keywords
application specific integrated circuits; circuit layout CAD; circuit optimisation; digital arithmetic; digital signal processing chips; integrated circuit layout; ASIC design; DSP hardware generation; area minimisation; fixed point DSP ASIC; hardware optimisation algorithm;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19960703
Filename
503075
Link To Document